Stephen R Hope (Docobo Ltd UK)

The concept of the internet of Things is something that is suddenly at the forefront of next generation technologies with the idea of billions of connected sensors providing a rich source of data for our everyday lives. This vision has now extended to the eHealth domain on the basis that this myriad of sensors will give indications about the health and wellbeing of a patient which will be used to make a diagnosis of the patient's condition by the clinician. Yet within the mountain of data the question has to be asked how much INFORMATION can be distilled that can actually be used by the clinician to care for an individual patient, i.e small data not big data methodologies whilst still meeting Information Governance requirements in respect of the need for medical device approval for devices making a medical diagnosis ; Also the need to know the provenance of any sensors that you may wish to use This presentation discusses the issues of IoT when operating in a medically regulated environment, the potential benefits and the possible downfalls. The presentation will also touch upon the fact that IoT is often talked about in the same breath as 5G with its targeted High Spectral efficiency and high bandwidth capabilities as a means of providing the perceived connectivity needs. Yet most potential sensors and devices in an eHealth environment potentially require limited bandwidth so another question also touched upon is does IoT need 5G in the context of the eHealth environment

 

A Dynamically Reconfigurable ECC Decoder Architecture for the next generation communication standards (5G, SDR and behond)

Cyrille Chavet (Université de Bretagne Sud & Lab-STICC, France); Philippe Coussy (Uniuversite de Bretagne-Sud / Lab-STICC, France)

The incoming communication standards (e.g. 5G, cognitive radio, SDR...) will be the origins of a deep revolution for the future of our widely connected world, with new communication scenarios, communications interoperability (e.g. wireless broadband, Internet of Things, Machine to Machine, Smart&Digital Factory...). As an example, contrary to 3G or 4G, the incoming 5G standard gathers several different radio signals (LTE-A, Wi-Fi/WISE…) in licensed or free bandwidth, in a combined heterogeneous and flexible network; also, in the defence and security domain, the advent of the Software Defined Radio (SDR) follows the operational logic of interoperability and cost-reductions to rationalise stocks of radio equipments, by implementing various waveforms on the same telecommunication equipment... This trend will be characterized by convergence of communication networks, melting several physical layers, several communication protocols (Wi-Fi, LTE, RFID tags...). This supposes to deal with several different channel codes, different consumption constraints, throughput targets...; in other words, this future world will be based on multiple radio (multi-RAT), allowing a dynamic adaptation in frequency, codes... and heterogeneous networks. In this context, channel decoding (i.e. FEC, Forward Error Correction) architecture is a critical element of such systems, since it impacts the quality of services (QoS), power consumption and the efficiency of radio resources usage. In order to limit the costs, either in terms of development cost or power consumption cost, an adaptive architecture that could deal with some (or all) of these applications/codes is extremely interesting. It also requires to be extensible (various throughput/latency targets) and flexible ECC architectures, i.e. supporting of several types of codes (turbo codes, LDPC, polar codes...) that can be changed dynamically during operation. However, the excellent performance of current FEC decoders comes at the expense of huge computational complexity. Hence, parallel architectures must be employed to speed up the decoding process and support required application throughputs. Moreover, several parameters such as scheduling, parallelism level, memory organization and network architecture need to be explored to tradeoff circuit area and performances. This requires the development of dedicated approaches to efficiently implement decoder architecture. In such implementation several Processing Elements (PEs) are used to obtain the required throughput. Memories are used to store different messages generated during the decoding process. These messages are written into and read out of the memories according to particular permutation defined by a permutation law. In order, to propose FEC decoder architectures that could meet the previous requirements, new architectural technologies must be explored. This contribution presents an innovative approach to design efficient, low-power, agile and dynamically reconfigurable ECC (Error Correction Codes) architectures in order to reduce the hardware cost and to support multiple standards with reduced memory footprint. In other words, our goal is to propose a single architecture that could be used to deal with all 5G communications and/or SDR and/or … for a minimized specialization overhead (hopefully for free). One of the problems, for example, is that such architectures suffer from memory access conflicts due to concurrent data accesses (from PEs to memories). This issue comes from the interleaving law in turbo-like codes or from the parity check matrix in LDPC. Different approaches have been developed to tackle this problem: definition of conflict-free data access orders, using dedicated hardware mechanisms to deal with conflicts at runtime, finding conflict free memory mappings at design time (off-chip) or more recently hybrid strategy that finds conflict free memory mappings on-chip at runtime. In parallel decoder architectures, design time approaches require storing into ROM the control words to drive the network and to address data memories for particular block length or/and interleaving law. So, in order to design flexible decoder architectures that support multiple block lengths and interleaving laws, multiple ROMs are needed which results in an important hardware overhead. Our proposed architecture is based on the implementation of a patented approach for FEC hardware architecture. Currently, it is clear that latency required to implement our algorithm is in compliance of existing telecommunication standards (4G LTE). However, the low architectural cost of our algorithm makes it suitable to embed on telecommunication and signal processing system for supporting multiple applications and standards (i.e. like in 5G, Cognitive Radio…).

On the Duality Between State-Dependent Channels and Wiretap Channels

David Kibloff (Univ Lyon, INRIA, INSA Lyon, CITI, France); Samir M. Perlaza (INRIA, France); Guillaume Villemaud (Université de Lyon, INRIA, INSA-Lyon, CITI, France); Leonardo S. Cardoso (Université de Lyon & INRIA, INSA-Lyon, CITI-INRIA, France)

In this work, the duality between state-dependent channels with causal channel state information at the transmitter and wiretap channels is established, and the conditions required for this duality to hold are given. Under these conditions, it is shown that an achievable scheme for the state-dependent channel is also an achievable scheme for the wiretap channel. Thus, results obtained for one model are shown to hold for the other. Moreover, it is found that for certain wiretap state-dependent channels with causal channel state information at the transmitter, secrecy is naturally guaranteed by the code construction for the state-dependent channel without requiring any additional effort to combat the eavesdropper.

 

Multi-standard OFDM transceiver for heterogeneous system-on-chips

Pascal Cotret (IETR, CentraleSupélec, France); Vipin Kizheppatt (Mahindra Ecole Centrale, India); Christophe Moy (CentraleSupelec/IETR, France)

The platform presented in this work emphasizes the use of software/hardware heterogeneous devices for flexible multi-RAT architectures. Hardware improvements are mainly focused on Dynamic Partial Reconfiguration (DPR) and especially reconfiguration speed. Management of the reconfiguration process is based on a Hierarchical and Distributed Cognitive Radio Architecture Management (HDCRAM). Some scenarios based on network centralized orders or power consumption decentral- ized orders will be explained. The demonstration is a baseband OFDM transceiver with some emulated white Gaussian noise channel. It functionnaly consists of three parts: a transmitter, a receiver, and an additive white Gaussian noise (AWGN) channel. The transmitter has two blocks: Mapping and Inverse Fast Fourier Transform (IFFT), and the receiver has also two corresponding blocks: Fast Fourier Transform (FFT) and Demapping. On the hardware point of view, the demonstration is implemented on a laptop and a Zynq platform (device including a hardcore processor and a FPGA).

 

A Phase Aligned Multi-Channel RF System Example

Ryan Koehn (National Instruments & BEEcube, USA); David Squires (National Instruments, USA)

Phase Aligned Multi-Channel RF Systems are a critical element in several application areas, including radar, direction finding, and massive MIMO. As technology in these areas evolves, there is an ever-growing need for more bandwidth and higher channel counts. These increasingly demanding system requirements necessitate a solution with both advanced IO synchronization capabilities and massive real time signal processing capacity. By combing high performing NI PXI RF instruments with the new NI FPGA ATCA Module for real time signal processing, it's possible to create multi-channel phase aligned systems that satisfy the performance requirements of some of the most challenging applications. This presentation develops a typical set of requirements for a phase aligned system with several GHz of aggregate processing bandwidth. A system architecture is created which satisfies these requirements and a specific implementation of such a system using off the shelf NI PXI and ATCA equipment is shown. Experimental results of this system are then presented.

 

Manuel Uhm (Ettus Research, a National Instruments Company, USA)

Note: This tutorial is two 90-min sessions. When developing software defined radio (SDR) platforms, the process is very different when the target is a general purpose processor (GPP) versus a FPGA based design. On GPP platforms, there are many powerful SDR suites, such as GNU Radio (GR), that provide a modular stream based processing infrastructure that allow the developer to focus on algorithm development. In these GPP SDR suites, the user is generally not required to be an expert in the low level infrastructure. Conversely, most FPGA platforms are monolithic implementations that require the user to be an expert in both their algorithm and the intimate details of the FPGA design's infrastructure. Furthermore, the FPGA platforms lack the GPP based SDR suite's ability to easily add, rearrange, and reconfigure processing blocks. However, FPGAs have tremendous parallel processing capability and can accelerate many SDR related algorithms. An ideal platform would allow heterogeneous processing with the GPP and FPGA while retaining the ease of design and flexibility of GPP based SDR. RF Network on Chip (RFNoC) is our implementation of such a platform. RFNoC is a new processing framework for Ettus Research third generation USRP devices that aims to make FPGA acceleration in SDR more accessible. RFNoC implements a packetized network infrastructure in the USRP's FPGA that handles the transport of control and sample data between the GPP and radio. Users implement their custom algorithms in FPGA based processing blocks, or Computation Engines (CEs), that attach to this network. CEs act as independent nodes on the network that can receive from and transmit data to any other node (such as another CE, radio frontend, or GPP.) This framework permits scalable designs that can distribute processing across many nodes. Users can create modular, FPGA accelerated SDR applications by chaining CEs into a flow graph in a fashion similar to many GPP SDR suites. One such suite, GNU Radio (GR), fully supports RFNoC. Users can create flow graphs containing both GR blocks and RFNoC CEs that seamlessly communicate. CE parameters, such as FFT size and FIR filter coefficients, can be set from within GNU Radio like any other GR block. By simplifying access to the FPGA, the same hardware can be more easily used for more demanding applications. We will present an in depth tutorial on RFNoC including a discussion on its design and capabilities, demos of several existing examples, and instructions on how to implement Computation Engines in RFNoC.

RFNoC (RF Network on Chip): Bringing the Power of the FPGA to GNU Radio

Manuel Uhm (Ettus Research, a National Instruments Company, USA)

Note: This tutorial is two 90-min sessions. When developing software defined radio (SDR) platforms, the process is very different when the target is a general purpose processor (GPP) versus a FPGA based design. On GPP platforms, there are many powerful SDR suites, such as GNU Radio (GR), that provide a modular stream based processing infrastructure that allow the developer to focus on algorithm development. In these GPP SDR suites, the user is generally not required to be an expert in the low level infrastructure. Conversely, most FPGA platforms are monolithic implementations that require the user to be an expert in both their algorithm and the intimate details of the FPGA design's infrastructure. Furthermore, the FPGA platforms lack the GPP based SDR suite's ability to easily add, rearrange, and reconfigure processing blocks. However, FPGAs have tremendous parallel processing capability and can accelerate many SDR related algorithms. An ideal platform would allow heterogeneous processing with the GPP and FPGA while retaining the ease of design and flexibility of GPP based SDR. RF Network on Chip (RFNoC) is our implementation of such a platform. RFNoC is a new processing framework for Ettus Research third generation USRP devices that aims to make FPGA acceleration in SDR more accessible. RFNoC implements a packetized network infrastructure in the USRP's FPGA that handles the transport of control and sample data between the GPP and radio. Users implement their custom algorithms in FPGA based processing blocks, or Computation Engines (CEs), that attach to this network. CEs act as independent nodes on the network that can receive from and transmit data to any other node (such as another CE, radio frontend, or GPP.) This framework permits scalable designs that can distribute processing across many nodes. Users can create modular, FPGA accelerated SDR applications by chaining CEs into a flow graph in a fashion similar to many GPP SDR suites. One such suite, GNU Radio (GR), fully supports RFNoC. Users can create flow graphs containing both GR blocks and RFNoC CEs that seamlessly communicate. CE parameters, such as FFT size and FIR filter coefficients, can be set from within GNU Radio like any other GR block. By simplifying access to the FPGA, the same hardware can be more easily used for more demanding applications. We will present an in depth tutorial on RFNoC including a discussion on its design and capabilities, demos of several existing examples, and instructions on how to implement Computation Engines in RFNoC.

NATO IST-140 RTG-065 Cognitive Radio Networks - Efficient Solutions for Routing, Topology Control, Data Transport, and Network Management

Stefan Couturier (Fraunhofer-Institut FKIE, Germany); Timo Bräysy (University of Oulu & Centre for Wireless Communications, Finland); Boyd Buchin (Rohde & Schwarz, Germany); Lorenza Giupponi (Centre Tecnològic de Telecomunicacions de Catalunya (CTTC), Spain); Jaroslaw Krygier (Military University of Technology, Poland); Vincent Le Nir (Royal Military Academy, Belgium); Topi Tuukkanen (Finnish Defence Research Agency, Finland); Erik Verheul (Royal Netherlands Navy, The Netherlands)

Cognitive Radio Networks is a topic of high relevance for both the civilian and the military world. According to literature, Cognitive Radio Networks are more than just a network of Cognitive Radios. While Cognitive Radios focus on finding the best frequencies to transmit messages to their neighbours (dynamic spectrum access), Cognitive Radio Networks aspire to transmit messages in the fastest, safest, and most efficient ways to their destinations (end-to-end optimization). Nevertheless, most of the current networking techniques have neither been designed for Cognitive Radio nor for military use. The ongoing NATO IST-140 research task group investigates challenges and solutions for Cognitive Radio Networks in a military context with regard to techniques like routing, topology control, network management, or exchange of control information. This presentation gives insights into the work of the group and its status.

Cognitive Radio: Thoughts and Projects 
Thierry Defaix (France DGA)

Introduction: France DGA Wirless Innovation Framework for Dual Applications
Presenter TBA

 

Enhanced air-ground communications in fast moving, multi-path environments

Olivier Rousset (Teamcast, France); Kevin Mille (Thales Communications & Security, France); Samuel Guillouard (TEAMCAST, France)

Air-ground communications in CAS (Close Air Support) applications are characterised by a fast moving transmitter (Aircraft) and a receiver sometimes located in an urban area, with many surrounding buildings acting as wave reflectors. In such situations, high speed data communications (e.g. for a video signal) using single carrier modulation are severely hampered by the echoes. Two French project associating the SME TeamCast and Thales Communications & Security have proposed enhancements for such applications. Both projects were supported by the French Ministry of Defence. The first project, ECHO, added an efficient channel equalizer on the receiver capable of cancelling echoes within a 5 µs time interval. This equalizer also handles high Doppler spread, up to 4 kHz, at the cost of sacrificing some net capacity by inserting reference patterns. The second project, MAXSIMO, added antenna diversity to the ECHO receiver in order to further improve the robustness of the transmission. In both projects, after proper channel models were defined, the algorithms were first refined through simulation, real-time demonstrators were built and the performances of the proposed solutions were verified through extensive laboratory testing using channel emulators. This presentation is about the results of the two projects. It shows the significant gains of transmission performance reached by the two complementary approaches.

 

Waveform Recognition for SDR based Radio Intrusion test platforms

Fatima Zohra Kaddour (SILICOM - France); Habib B.A. Sidi (INRIA, France); Mehrez Selmi (SILICOM, France)

Programmable radio systems and low-cost devices with sufficient computational power have fostered the development of Software Defined Radio (SDR) which is experiencing a rapid growth. Since the SDR can change its function by changing the software, the hacking procedure could be developed without investing in expensive hardware or circuitry-making equipment. The objective of the TIRAD project is to develop an agile SDR platform to test radio intrusion and elaborate attacks on various wireless communication systems. The developed platform is based on existing tools from the GnuRadio project and low-cost devices such as Universal Software Radio Peripheral (USRP) N210. The main challenge in developing such system is the capability to detect and identify anonymous communications covering a large range of wireless communication technologies. Thus, the platform is based on a sniffing procedure that detects a wireless transmission and provides to the hacking procedure the main characteristics of the waveform. We focus on a semi blind recognition algorithm. This later is based on the constructed waveform ontology (i.e., data base) that contains the main characteristics of several wireless systems such as, the frequency bands, the modulation types or preambles. This recognition is based in three main steps: (i) spectrum analysis: this consists of a sniffing procedure that scans the frequency spectrum in order to detect an eventual transmission using the energy thresholding method and identify both the occupied frequency band and the carrier frequency. The bins averaging technique is considered in order to increase frequency detection accuracy and prevents false peaks errors. Hence, based on the frequency bands information and the waveform ontology, a subset of a standard candidate is selected. However, this may be insufficient to fully recognize the transmitted waveform. Therefore, the two additional steps are performed: (ii) synchronization: which consists of detecting the preambles of the standard candidates given in the ontology, and (iii) demodulation: that reads some frame fields such as start frame delimiters and comparing them with the pre-recorded information. At the end of each step the subset of candidate wireless standards is short-listed. Finally, upon executing these successive steps, the waveform recognition result is given and the characteristics of the transmitted signal are depicted. The hacking procedure can then exploit the recognized waveform information to perform attacks. In the framework of this project, two wireless communication systems are hacked: (i) WiFi: by emulating a virtual access point, and (ii) ZigBee: where On/Off messages are sent to smart home plugs.

COMET Project: The COMET RAPID project, a contribution to the Unified Component Model (UCM) OMG standard
Thomas Vergnaud and Olivier Hachet (Thales)

For more than a decade, component-based software engineering has been considered a key enabler to increase software reuse and reduce time to market. In particular, several companies have adopted component-based software engineering for embedded real time or critical system. Due to the domain constraints, these companies have built their own component model and associated frameworks or have made significant adaptations to existing standards like to the lightweight CORBA Component Model standardized from OMG. Considering this example, the use of the LwCCM in embedded applications can lead to an undesired memory and storage footprint with its  mandatory dependency on CORBA, avoiding usage of alternative middleware implementations. Moreover, most of the existing other component models are usually defined with a specific underlying middleware and the associated execution semantic that do not fit all DRTE environments. COMET is a RAPID project executed by Thales and Prismtech. It stands for “COmponent Model for distributed, Embedded real Time systems” and aims at defining a multi-domain component framework for embedded systems. It has strongly influenced the UCM standardization for a simple, lightweight, middleware-agnostic, and flexible component model taking into account DRTE concerns like mastering memory, defining specific interaction patterns, introducing mechanism to master non-functional properties.

Defining and using Standard Transceiver APIs: 10 years of lessons learnt

Eric Nicollet (Thales, France)

The presentation will share 10 years of lessons learnt in various efforts aimed at definition and usage of standard Transceiver APIs. Definition aspects will namely refer to: the PEA AL; the CP277 submitted in 2005 for SCA 3.0; the response to the OMG Digital IF RFP; the WInnF Transceiver Facility V1; the ESSOR Transceiver API; the WInnF Transceiver Next project. Usage reports will be based on: the PEA AL, WINTSEC, ESSOR studies, plus stories taken from products development experiences.

SDR Application portability: experiences and perspectives

Eric Nicollet, Yves-André Caparros, Jean-Julien Sabiani and Frédéric Dotto (Thales, France)

Encompassing the whole range of waveform capabilties, from Protocol layers down to PHysical layers, the presentation will share perpectives from Thales development teams regarding porting experiences and perspectives. The discussion is taking the ESSOR Porting Methodology as basis for discussion, grounded on the ESSOR and on-going development experiences. Concept, benefit and practices attached to the concept of Base Waveform are given particular attention.

EDA Perspective on SDR standards
Philippe Cambraye (EDA)

ETSI Reconfigurable Radio Systems (RRS) role and activies
Markus Mueck (Intel)